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features ? advanced, high-speed, electrically-erasable programmable logic device ? superset of 22v10 ? enhanced logic flexibility ? backward compatible with atv750b/bl and atv750/l low-power edge-sensing ?l? option with 1 ma standby current d- or t-type flip-flop product term or direct input pin clocking 7.5 ns maximum pin-to-pin delay with 5v operation highest density programmable logic available in 24-pin package ? advanced electrically-erasable technology ? reprogrammable ? 100% tested increased logic flexibility ? 42 array inputs, 20 sum terms and 20 flip-flops enhanced output logic flexibility ? all 20 flip-flops feed back internally ? 10 flip-flops are also available as outputs programmable pin-keeper circuits dual-in-line and surface mount package in standard pinouts commercial and industrial temperature ranges 20-year data retention 2000v esd protection 1000 erase/write cycles block diagram description the atf750c(l)s are twice as powerful as most other 24-pin programmable logic devices. increased product terms, sum terms, flip-flops and output logic configurations programmable interconnect and combinatorial logic array logic option (up t0 20 flip-flops) output option 4to8 product terms (oe product terms) 10 i/o pins 12 input pins (clock pin) high-speed complex programmable logic device atf750c ATF750CL 0776i?pld?3/04 note: for plcc, pins 1, 8, 15, and 22 can be left unconnected. for superior performance, connect vcc to pin 1 and gnd to pins 8, 15, and 22. pin configurations pin function clk clock in logic inputs i/o bi-directional buffers gnd ground vcc +5v supply dip/soic/tssop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/in in in in in in in in in in in gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o in plcc 5 6 7 8 9 10 11 25 24 23 22 21 20 19 in in in gnd * in in in i/o i/o i/o gnd * i/o i/o i/o 4 3 2 1 28 27 26 12 13 14 15 16 17 18 in in gnd gnd * in i/o i/o in in clk/in vcc * vcc i/o i/o
2 atf750c/cl 0776i?pld?3/04 translate into more usable gates. high-speed logic and uniform predictable delays guar- antee fast in-system performance. the atf750c(l) is a high-performance cmos (electrically-erasable) complex programmable logic device (cpld) that utilizes atmel?s proven electrically-erasable technology. each of the atf750c(l)?s 22 logic pins ca n be used as an input. ten of these can be used as inputs, outputs or bi-directional i/ o pins. each flip-flop is individually config- urable as either d- or t-type. each flip-flop output is fed back into the array independently. this allows burying of all the sum terms and flip-flops. there are 171 total product terms available. there are two sum terms per output, pro- viding added flexibility. a variable format is used to assign between four to eight product terms per sum term. much more logic can be replaced by this device than by any other 24-pin pld. with 20 sum terms and flip-flops, complex state machines are easily imple- mented with logic to spare. product terms provide individual clocks and asynchronous resets for each flip-flop. each flip-flop may also be individually configured to have direct input pin controlled clocking. each output has its own enable product term. one product term provides a common synchronous preset for all flip-flops. register preload functions are provided to simplify testing. all registers automatically reset upon power-up. the atf750c(l) is a low-power device with speeds as fast as 15 ns. the atf750c(l) provides the optimum low-power cpld solution. this device significantly reduces total system power, thereby allowing battery-powered operations. dc and ac operating conditions all members of the family are specified to operate in either one of two voltage ranges. parameters are specified as noted to be either 2.7v to 3.6v, 5v 5% or 5v 10%. absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) 5v operation commercial -7.5, -10, -15 industrial -10, -15 operating temperature (ambient) 0c - 70c -40c - +85c v cc power supply 5v 5% 5v 10%
3 atf750c/cl 0776i?pld?3/04 logic options clock mux output options combinatorial output registered output combined terms separate terms combined terms separate terms select logic to cell clock product term clk cki ckmux pin
4 atf750c/cl 0776i?pld?3/04 bus-friendly pin-keeper input and i/os all input and i/o pins on the atf750c(l) have programmable ?pin-keeper? circuits. if activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption. enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. please refer to the software compiler table for more details. once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and i/os. . input diagram i/o diagram table 1. software compiler mode selection synario wincupl pin-keeper circuit atf750c v750c disabled atf750c (ppk) v750cppk enabled 100k v cc esd protection circuit input programmable option 100k v cc v cc data oe i/o programmable option
5 atf750c/cl 0776i?pld?3/04 note: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. input test waveforms and measurement levels t r , t f < 3 ns (10% to 90%) output test load dc characteristics symbol parameter condition min typ max units i li input load current v in = -0.1v to v cc + 1v 10 a i lo output leakage current v out = -0.1v to v cc + 0.1v 10 a i cc power supply current, standby v cc = max, v in = max, outputs open c-7, -10 com. 125 180 ma ind., mil. 135 190 ma c-15 com. 125 180 ma ind., mil. 135 190 ma cl-15 com. 0.12 1 ma ind., mil. 0.15 2 ma i os (1) output short circuit current v out = 0.5v -120 ma v il input low voltage 4.5 v cc 5.5v -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il , v cc = min i ol = 16 ma com., ind. 0.5 v i ol = 12 ma mil. 0.5 v i ol = 24 ma com. 0.8 v v oh output high voltage v in = v ih or v il , v cc = min i oh = -4.0 ma 2.4 v vcc 390 (750 mil.) 300 (390 mil.)
6 atf750c/cl 0776i?pld?3/04 ac waveforms, product term clock (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. note: 1. see ordering information for valid part numbers. ac characteristics, product term clock (1) symbol parameter -7 -10 c/cl-15 units min max min max min max t pd input or feedback to non-registered output 7.5 10 15 ns t ea input to output enable 7.5 10 15 ns t er input to output disable 7.5 10 15 ns t co clock to output 3 7.5 4 10 5 12 ns t cf clock to feedback 1 5 4 7.5 5 9 ns t s input setup time 3 4 8/12 ns t sf feedback setup time 3 4 7 ns t h hold time 125ns t p clock period 7 11 14 ns t w clock width 3.5 5.5 7 ns f max external feedback 1/(t s + t co )957150/41mhz internal feedback 1/(t sf + t cf ) 125 86 62 mhz no feedback 1/(t p ) 142 90 71 mhz t aw asynchronous reset width 5 10 15 ns t ar asynchronous reset recovery time 3 10 15 ns t ap asynchronous reset to registered output reset 8 12 15 ns t sp setup time, synchronous preset 4 7 8 ns
7 atf750c/cl 0776i?pld?3/04 ac waveforms, input pin clock (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. ac characteristics, input pin clock symbol parameter -7 -10 c/cl-15 units min max min max min max t pd input or feedback to non-registered output 7.5 10 15 ns t ea input to output enable 7.5 10 15 ns t er input to output disable 7.5 10 15 ns t cos clock to output 0 6.5 0 7 0 10 ns t cfs clock to feedback 0 3.5 0 5 0 5.5 ns t ss input setup time 4 5 8/12.5 ns t sfs feedback setup time 4 5 7 ns t hs hold time 000ns t ps clock period 7 10 12 ns t ws clock width 3.5 5 6 ns f maxs external feedback 1/(t ss + t cos )958355/44mhz internal feedback 1/(t sfs + t cfs ) 133 100 80 mhz no feedback 1/(t ps ) 142 100 83 mhz t aw asynchronous reset width 5 10 15 ns t ars asynchronous reset recovery time 5 10 15 ns t ap asynchronous reset to registered output reset 8 10 15 ns t sps setup time, synchronous preset 5 5/9 11 ns
8 atf750c/cl 0776i?pld?3/04 functional logic diagram atf750c, upper half
9 atf750c/cl 0776i?pld?3/04 functional logic diagram atf750c, lower half
10 atf750c/cl 0776i?pld?3/04 preload of registered outputs the atf750c(l)?s registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. this feature will simplify testing since any state can be forced into the registers to control test sequencing. a v ih level on the i/o pin will force the register high; a v il will force it low, independent of the output polarity. the preload state is entered by placing a 10.25v to 10.75v signal on pin 8 on dips, and lead 10 on smds. when the clock term is pulsed high, the data on the i/o pins is placed into the register chosen by the select pin. level forced on registered output pin during preload cycle select pin state register #0 state after cycle register #1 state after cycle v ih low high x v il low low x v ih high x high v il high x low
11 atf750c/cl 0776i?pld?3/04 power-up reset the registers in the atf750c(l)s are designed to reset during power-up. at a point delayed slightly from v cc crossing v rst , all registers will be reset to the low state. the output state will depend on the polarity of the output buffer. this feature is critical for state machine initialization. however, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. the clock pin, or signals from which clock terms are derived, must remain stable during t pr . note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. parameter description typ max units t pr power-up reset time 600 1000 ns v rst power-up reset voltage 3.8 4.5 v pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 58 pfv in = 0v c out 68 pfv out = 0v
12 atf750c/cl 0776i?pld?3/04 using the atf750c?s many advanced features the atf750c(l)?s advanced flexibility packs mo re usable gates into 24 pins than any other logic device. the atf750c(l)s start with the popular 22v10 architecture, and add several enhanced features: selectable d- and t-type registers each atf750c(l) flip-flop can be individually configured as either d- or t-type. using the t-type configuration, jk and sr flip-flops are also easily created. these options allow more efficient product term usage. selectable asynchronous clocks each of the atf750c(l)?s flip-flops may be clocked by its own clock product term or directly from pin 1 (smd lead 2). this removes the constraint that all registers must use the same clock. buried state machines, counters and registers can all coexist in one device while running on separate clocks. individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. a full bank of ten more registers the atf750c(l) provides two flip-flops per output logic cell for a total of 20. each register has its own sum term, its own reset term and its own clock term. independent i/o pin and feedback paths each i/o pin on the atf750c(l) has a dedicated input path. each of the 20 registers has its own feedback terms into the array as well. this feature, combined with individual product terms for each i/o?s output enable, facilitates true bi- directional i/o design. synchronous preset and asynchronous reset one synchronous preset line is provided for all 20 registers in the atf750c(l). the appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. appropriate setup and hold times must be met, as shown in the switching waveform diagram. an individual asynchronous reset line is provided for each of the 20 flip-flops. both mas- ter and slave halves of the flip-flops are reset when the input signals received force the internal resets high. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf750c(l) fuse pat- terns. once the security fuse is progra mmed, all fuses will appear programmed during verify. the security fuse should be programmed last, as its effect is immediate.
13 atf750c/cl 0776i?pld?3/04 atf750c supply current vs. supply voltage (t a = 25c) 0 20 40 60 80 100 120 140 4.50 4.75 5.00 5.25 5.50 supply voltage (v) i cc (ma) atf750c supply current vs. supply voltage (t a = 25c) 0 20 40 60 80 100 120 140 4.50 4.75 5.00 5.25 5.50 supply voltage (v) i cc (ma) ATF750CL supply current vs. supply voltage (t a = 25c) 0 20 40 60 80 100 120 140 160 4.50 4.75 5.00 5.25 5.50 supply voltage (v) i cc (a) supply current vs. frequency standard power (t a = 25c) 0 40 80 120 160 0 5 10 25 50 75 100 frequency (mhz) i cc (ma) supply current vs. frequency low-power ("l") version (t a = 25c) 0 20 40 60 80 100 120 140 0 5 10 25 50 75 100 frequency (mhz) i cc (ma) atf750c/cl output source current vs. supply voltage (v oh = 2.4v) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 44.555.56 supply voltage (v) i oh (ma) atf750c/cl output source current vs. output voltage (v cc = 5v, t a = 25c) -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 v oh (v) i oh (ma)
14 atf750c/cl 0776i?pld?3/04 atf750c/cl output sink current vs. supply voltage (v ol = 0.5v) 34 35 36 37 38 39 40 41 42 43 44 44.555.56 supply voltage (v) i ol (ma) atf750c/cl output sink current vs. output voltage (v cc = 5v, t a = 25c) 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v ol (v) i ol (ma) atf750c/cl output sink current vs. output voltage (v cc = 5v, t a = 25c) 0 10 20 30 40 50 60 70 80 90 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 v ol (v) i ol (ma) a tf750c/cl input current vs. input voltage (v cc = 5v,t a = 25c) -25 -20 -15 -10 -5 0 5 10 15 20 25 30 00.511.522.533.544.555.56 input voltage (v) input current (ua) atf750c/cl input current vs. input voltage (v cc = 5v,t a = 25c) without pin-keeper -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 input voltage (v) input current (ua) atf750c/cl input clamp current vs. input voltage (v cc = 5v,t a = 35c) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 -0.2 -0.4 -0.6 -0.8 -1 input voltage (v) input current (ma)
15 atf750c/cl 0776i?pld?3/04 note: 1. special order only: tssop package requires special thermal management. using ?c? product for industrial to use commercial product for industrial ranges, down-grade one speed grade from the ?i? to the ?c? device (7 ns ?c? = 10 ns ?i?) and de-rate power by 30%. atf750c(l) ordering information t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code package operation range 7.5 6.5 95 atf750c-7jc at f 7 5 0 c - 7 p c at f 7 5 0 c - 7 s c at f 7 5 0 c - 7 x c (1) 28j 24p3 24s 24x (1) commercial (0 c to 70 c) 10 7 83 atf750c-10jc atf750c-10pc atf750c-10sc atf750c-10xc (1) 28j 24p3 24s 24x (1) commercial (0 c to 70 c) atf750c-10ji atf750c-10pi atf750c-10si 28j 24p3 24s industrial (-40 c to 85 c) 15 10 55 atf750c-15jc atf750c-15pc atf750c-15sc atf750c-15xc (1) 28j 24p3 24s 24x (1) commercial (0 c to 70 c) atf750c-15ji atf750c-15pi atf750c-15si 28j 24p3 24s industrial (-40 c to 85 c) 15 10 44 ATF750CL-15jc ATF750CL-15pc ATF750CL-15sc ATF750CL-15xc (1) 28j 24p3 24s 24x (1) commercial (0 c to 70 c) ATF750CL-15ji at f 7 5 0 c l - 1 5 p i at f 7 5 0 c l - 1 5 s i 28j 24p3 24s industrial (-40 c to 85 c) package type 28j 28-lead, plastic j-leaded chip carrier (plcc)
16 atf750c/cl 0776i?pld?3/04 24p3 24-lead, 0.300" wide, plastic dual inline package (pdip) 24s 24-lead, 0.300" wide, plastic gull wing small outline (soic) 24x (1) 24-lead, 0.173" wide, thin shrink small outline (tssop) package type
17 atf750c/cl 0776i?pld?3/04 packaging information 28j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. b 28j , 28-lead, plastic j-leaded chip carrier (plcc) 28j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-018, variation ab. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 4.572 a1 2.286 3.048 a2 0.508 d 12.319 12.573 d1 11.430 11.582 note 2 e 12.319 12.573 e1 11.430 11.582 note 2 d2/e2 9.906 10.922 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ
18 atf750c/cl 0776i?pld?3/04 24p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 24p3 , 24-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) c 24p3 09/28/01 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a 5.334 a1 0.381 d 31.623 ? 32.131 note 2 e 7.620 8.255 e1 6.096 7.112 note 2 b 0.356 0.559 b1 1.270 1.551 l 2.921 3.810 c 0.203 0.356 eb 10.922 ec 0.000 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation af. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
19 atf750c/cl 0776i?pld?3/04 24s ? soic 0o ~ 8o pin 1 id pin 1 06/17/2002 2325 orchard parkway san jose, ca 95131 title drawing no. rev. 24s , 24-lead (0.300" body) plastic gull wing small outline (soic) b 24s r common dimensions (unit of measure = mm) symbol min nom max note a ? ? 2.65 a1 0.10 ? 0.30 d 10.00 ? 10.65 d1 7.40 ? 7.60 e 15.20 ? 15.60 b 0.33 ? 0.51 l 0.40 ? 1.27 l1 0.23 ? 0.32 e 1.27 bsc b d d1 e e a a1 l1 l
20 atf750c/cl 0776i?pld?3/04 24x ? tssop 0.30(0.012) 0.19(0.007) 4.48(0.176) 4.30(0.169) 6.50(0.256) 6.25(0.246) 0.65(0.0256)bsc 7.90(0.311) 7.70(0.303) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018) 0o ~ 8o 1.20(0.047)max dimensions in millimeter and (inches)* jedec standard mo-153 ad controlling dimension: millimeters pin 1 04/11/2001 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 24x , 24-lead (4.4 mm body width) plastic thin shrink small outline package (tssop) a 24x
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